1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to methods of forming a semiconductor structure wherein an annealing process is performed to activate and/or diffuse dopants introduced into a feature formed over a substrate.
2. Description of the Related Art
Integrated circuits comprise a large number of individual circuit elements, such as transistors, capacitors and resistors. These elements are connected by means of electrically conductive lines to form complex circuits such as memory devices, logic devices and micro-processors. The performance of integrated circuits may be improved by increasing the number of functional elements per circuit in order to increase the circuit's functionality and/or by increasing the speed of operation of the circuit elements. A reduction of feature sizes allows the formation of a greater number of circuit elements on the same area, hence increasing the functionality of the circuit, and also reducing signal propagation delays, thus making an increase of the speed of operation of circuit elements possible. Reducing the size of circuit elements such as field effect transistors, however, entails a plurality of issues associated therewith that need to be addressed.
A method of forming a field effect transistor according to the state of the art will be described with reference to FIGS. 1a-1c. FIG. 1a shows a schematic cross-sectional view of a semiconductor structure 100 in a first stage of a method of manufacturing a semiconductor structure according to the state of the art.
The semiconductor structure 100 comprises a substrate 101 which may, for example, comprise a silicon wafer. The substrate 101 may comprise a transistor element 102. The transistor element 102 may comprise an active region 104 which may be formed, for example, by means of techniques of ion implantation well known to persons skilled in the art. As persons skilled in the art know, the doping of the active region 104 may be performed by implanting ions of a dopant material into the substrate 101. A trench isolation structure 103 provides electrical insulation between the transistor element 102 and other circuit elements (not shown) in the semiconductor structure 100. The trench isolation structure 103 may be formed by means of techniques of photolithography, etching, deposition and/or oxidation well known to persons skilled in the art.
The transistor element 102 may further comprise a gate electrode 106 separated from the active region 104 by a gate insulation layer 105. The gate insulation layer 105 may comprise an electrically insulating material such as, for example, silicon dioxide, silicon nitride and/or silicon oxynitride. The gate electrode 106 may, in some examples of methods of forming a semiconductor structure according to the state of the art, comprise polysilicon. The gate insulation layer 105 and the gate electrode 106 may be formed by means of techniques of oxidation, nitridation, deposition and etching that are well known to persons skilled in the art.
After the formation of the gate electrode 106, an ion implantation process may be performed. In the ion implantation process, the semiconductor structure 100 is irradiated with ions of a dopant material, as indicated by arrows 107 in FIG. 1a. A portion of the ions 107 impinging adjacent the gate electrode 106 may be incorporated into the substrate 102 to form an extended source region 108 and an extended drain region 109. Ions 107 impinging on the gate electrode 106 may be absorbed by the gate electrode 106. Hence, substantially no ions are introduced into a portion of the substrate 101 below the gate electrode 106 wherein a channel region of the transistor element 102 is to be formed. The ions absorbed by the gate electrode 106 may form a first doped region 110 in the gate electrode 106.
FIG. 1b shows a schematic cross-sectional view of the semiconductor structure 100 in a later stage of the manufacturing process according to the state of the art. After the formation of the extended source region 108 and the extended drain region 109, a sidewall spacer structure 120 may be formed adjacent the gate electrode 106. As persons skilled in the art know, the sidewall spacer structure 120 may be formed by conformally depositing a layer of an electrically insulating spacer material such as silicon dioxide, silicon oxynitride and/or silicon nitride and anisotropically etching the layer of the spacer material.
Thereafter, a further ion implantation process wherein the semiconductor structure 100 is irradiated with ions 111 of a dopant material may be performed. A portion of the ions 111 impinging adjacent the gate electrode 106 and the sidewall spacer structure 120 may be incorporated into the substrate 101 to form a source region 112 and a drain region 113. A portion of the ions 111 impinging on the gate electrode 106 may be incorporated into the gate electrode 106 to form a second doped region 114 in the gate electrode 106.
FIG. 1c shows a schematic cross-sectional view of the semiconductor structure 100 in a later stage of the manufacturing process according to the state of the art. After the implantation of the ions 111, an annealing process may be performed. In the annealing process, the semiconductor structure 100 may be exposed to an elevated temperature for a predetermined time, for example by inserting the semiconductor structure 100 into a furnace, or by performing a rapid thermal annealing process well known to persons skilled in the art. In the annealing process, the dopants in the extended source region 108, the extended drain region 109, the source region 112, the drain region 113, the first doped region 110 and the second doped region 114 may be incorporated into the crystalline structure of the substrate 101 and the gate electrode 106, respectively, such that they may act as electron donors or acceptors. Furthermore, the dopants may diffuse in the substrate 101 and in the gate electrode 106.
In the substrate 101, which may comprise substantially monocrystalline silicon, the diffusion of the dopants may lead to a blurring of the dopant profile in the extended source region 108, the extended drain region 109, the source region 112 and the drain region 113 created by the implantation of the ions 107, 111. In the gate electrode 106, due to the diffusion of the dopants introduced into the first doped portion 110 and the second doped portion 114, a dopant-rich region 115 may be formed, wherein the extension of the dopant-rich region 115 may differ from the extension of the doped portions 110, 114. Since the dopants may diffuse into portions of the gate electrode 106 in the vicinity of the gate insulation layer 105 only to a limited extent, a region 116 comprising a reduced dopant concentration may be formed in the gate electrode 106 adjacent the gate insulation layer 105.
As persons skilled in the art know, in the operation of the transistor element 102, the gate electrode 106 may be biased to form an inversion layer in a portion of the active region 104 below the gate electrode 106. Due to the reduced dopant concentration in the region 116 of the gate electrode 106, a depletion layer may be formed in the gate electrode 106 adjacent the gate insulation layer 105. The presence of the depletion layer, which may be detected by measuring an inversion gate insulation thickness of the transistor element 102 by means of methods known to persons skilled in the art, may lead to a reduced capacitive coupling between the gate electrode 106 and the channel region formed adjacent the gate insulation layer 105, which may reduce the performance of the transistor element 102.
In the state of the art, it has been proposed to reduce the size of the region 116 comprising the reduced dopant concentration and, hence, the thickness of the depletion layer, by performing a flash lamp annealing or a laser annealing in addition to the furnace annealing process or rapid thermal annealing process described above. The flash lamp or laser annealing process may be performed after the annealing process described above, or after the irradiation of the semiconductor structure 100 with the ions 107, 111. The flash lamp or laser annealing process may induce a diffusion of dopants in the gate electrode 106. Thus, dopant atoms may diffuse into portions of the region 116 comprising the reduced dopant concentration such that the size of the region 116 is reduced. Hence, in the operation of the transistor element 102, the size of the depletion region formed in the gate electrode 106 and the inversion gate insulation thickness associated therewith may be reduced.
Experiments have shown that the additional flash annealing process or laser annealing process, respectively, may improve the performance of N-type field effect transistors. In P-type field effect transistors, however, only a small improvement of the DC performance, which may be determined by measuring a relationship between the saturation current of the transistor and the off-state current of the transistor, may be observed. Moreover, in P-type transistors, the additional flash annealing process or laser annealing process may lead to an increased parasitic gate capacitance and to an increased dynamic power consumption of the transistor element 102. Furthermore, an increase of the gate leakage by about 10-20% may be observed in P-type transistors, which may be attributed to an increase of the electric field strength at the gate insulation layer 105. Hence, the additional flash lamp annealing or laser annealing process may adversely affect the performance of P-type transistor elements.
Therefore, the method of manufacturing a semiconductor structure according to the state of the art, wherein an additional flash lamp annealing process or laser annealing process is performed, which may be used to improve the performance of N-type transistors, may adversely affect the performance of P-type transistors.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.